It is known that when the supply voltage (e.g., VDD) of a voltage regulator ramps up after the source of the supply power is powered on, the regulator output voltage can quickly snap up (i.e., quickly rise) to an intermediate voltage depending on the reference current generator design and/or the regulator design. This snap up condition is problematic if the regulator has a resistor-capacitor (RC) triggered electrostatic discharge (ESD) clamp on its load and if the regulator snaps up fasterthan the RC time constant of the ESD clamp. In this scenario, the ESD clamp will turn on and generate very large currents that can damage the regulator. In another scenario, the ESD clamp turning on will cause no voltage to be output by the regulator.
Existing solutions to the above-described snap-up problem typically use some form of soft-start charging capacitor and current source in order to insure a slow ramp-up of the regulator. However, if the charging capacitor is provided as an external component, then the cost and space requirements of the regulator are disadvantageously increased. On the other hand, if the charging capacitor is provided as an integrated circuit component, then the die area is disadvantageously increased.
It is therefore desirable to avoid the aforementioned excessive current flow during the start-up of a voltage regulator without requiring a charging capacitor.